The present invention relates in general to switched capacitor circuits and in particular to circuits and methods for linearizing capacitor calibration and systems using the same.
One particular technique for performing analog to digital (A/D) conversion is through successive approximation. The basic successive approximation A/D converter (ADC) includes an analog comparator and a clocked feedback loop having a successive approximation register (SAR) and a digital to analog converter (DAC).
Generally, the analog input signal voltage is sampled onto an array of weighted capacitors, during the sampling phase, the top plates of which are coupled to one comparator input. The other comparator input is coupled to a comparison voltage, which could be a fixed reference voltage in a single-ended system or the voltage at the top plates of second capacitor array in a differential system.
During the first clock cycle of the subsequent conversion phase, the bottom plate of the capacitor representing the digital MSB is coupled to a reference voltage while the bottom plates of the remaining capacitors in the array are coupled to ground or a second reference voltage (ground will be assumed here). The new top plate voltage appears at the input of the comparator and is compared against the comparison voltage. If the new top plate voltage is below the comparison voltage, then the MSB is xe2x80x9ckeptxe2x80x9d by the SAR in the feedback loop by maintaining its bottom plate coupled to the reference voltage. On the other hand, if the top plate voltage is above the comparison voltage, the SAR couples and the bottom plate of the MSB capacitor to ground. The state of the MSB capacitor represent the MSB of the digital output word as a Logic 1. The bottom plate of the second MSB is then coupled to the reference voltage and the same test is performed to determine the state of the next digital code bit. The successive approximation algorithm continues by repeating this procedure for the remaining capacitors in the array such that the voltage difference at the inputs to the comparator converge to zero. At the end of this bit cycling process, the configuration of the switches coupling the bottom plates either to Vref or Gnd represents the input sample in digital form.
Successive approximation AID converters are useful a wide range of applications, including data acquisition, test equipment, instrumentation, cellular communications, among others. Notwithstanding, in order to improve and broaden the utility of this type of A/D converter, significant challenges remain to be addressed. These challenges include improving the device speed given a set of process constraints, reducing the coding error rate, handling metastable states and device calibration
The inventive concepts allow for the compensation for varying voltage offsets appearing at a node in a switched capacitor circuit. These offsets may be caused, for example, by switch charge injection during the process of sampling a voltage onto the node, the charge injection varying as a function of the impedance appearing at the node at a given instant. These concepts are particularly useful with respects to capacitor arrays having one or more capacitors associated with a trim array, the trim array changing the impedance at a common node as trim capacitors are selectively used during trimming operations.
According to one specific embodiment of the principles of the present invention, a switched capacitor circuit is disclosed which includes a plurality of capacitor arrays coupled to a node, including an input array, a trim array associated with a selected capacitor of the input array, and an offset compensation array. A first set of switches are selectively used to couple capacitors of the input and trim arrays to selected reference voltages to approximate an impedance presented at the node during a subsequent operation to trim the selected capacitor of the input array. A sampling switch is included for sampling the selected reference voltages onto the input and trim arrays, the sampling switch injecting a corresponding amount of charge onto the node. This charge injection mismatch between the +ve and xe2x88x92ve array top plates coil appears as a code dependent offset to the trim cap calibration system. A second set of switches then selectively couples capacitors of the offset compensation array to the selected reference voltages to compensate for the amount of charge injected on the node by the sampling switch.
Advantageously, the present inventive concepts allow for a voltage offset resulting from charge injection onto a node during voltage sampling to be compensated for as each capacitor in the primary array is trimmed. Moreover, in circuits also including a comparator, any voltage offset introduced by that comparator can also be compensated for concurrently.